Two billion dollars for chipmaker Cerebras within four months

"American AI chip developer Cerebras Systems has once again raised $1 billion in growth capital. This is a Series H financing round that values the company at approximately $23 billion. The investment comes remarkably quickly after a previous capital round of $1.1 billion, which was completed just four months ago. The new round was led by Tiger Global. Benchmark, Fidelity Management & Research Company, Atreides Management, Alpha Wave Global, Altimeter, Coatue, 1789 Capital, and chip manufacturer AMD, among others, also participated."

"Cerebras has distinguished itself for years with a different chip architecture. Instead of building AI accelerators from multiple separate chips, the company develops processors that consist of a single complete silicon wafer. According to the company, the current generation, the Wafer Scale Engine 3, contains approximately four trillion transistors. That is many times more than modern GPUs, such as Nvidia's Blackwell B200."

"Approximately half of the chip surface is reserved for an internal SRAM memory pool of 44 gigabytes. This allows many AI models to run entirely on the chip without constantly moving data to external HBM memory. This reduces delays that normally occur due to data transport between the processor and memory and should significantly speed up processing. Wafer-scale chips have historically been rarely built due to manufacturing problems."

Cerebras closed a $1 billion Series H financing round at an approximate $23 billion valuation, coming four months after a $1.1 billion round. The round was led by Tiger Global with participation from investors including Benchmark, Fidelity Management & Research Company, Atreides Management, Alpha Wave Global, Altimeter, Coatue, 1789 Capital, and AMD. The timing aligns with reports of a multiyear hardware supply agreement with OpenAI worth over $10 billion. Cerebras produces wafer‑scale processors (WSE‑3) of a single silicon wafer with roughly four trillion transistors and a 44 GB on‑chip SRAM pool to reduce data‑transfer latency. Wafer‑scale manufacturing risks are mitigated by dividing the WSE‑3 into many separate cores.

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